1. Field of the Invention
The present invention relates to a signal transmission, and more particularly, to a signal transmission technique by a differential input/output circuit.
2. Description of Related Art
Along with current advancement of an LSI (large-scale integrated circuit) manufacturing technique, a high-performance MPU (Micro Processor Unit) whose operating frequency exceeds 1 GHz has been developed. When such an MPU is employed in an information processing device or especially a server/workstation, high-speed and large amount of data transmission is needed. In order to achieve this, a system connecting the MPU with each module of a memory by PTP (Point-to-Point) employing an FB-DIMM (Fully Buffered Dual Inline Memory Module) has been used, for example. The FB-DIMM includes an AMB (Advanced Memory Buffer) chip for connection between modules mounted thereon in addition to a memory chip, and employs high-speed serial interface standard “FB-DIMM High Speed Differential PTP Link at 1.5 V” as a connection interface.
A terminating resistor is typically provided in a transceiver in consideration of an impedance matching in order to prevent influence of reflection due to the transmission path length in high-speed transmission.
FIG. 7 shows an example of a differential transceiver having terminating resistors provided therein. The differential transceiver includes a differential transmitter block 20, a differential receiver block 30, and an idle state detector block 40.
The differential transmitter block 20 includes a constant current source 22, N channel transistors (hereinafter referred to as N transistors) 23a and 23b receiving a constant current from the constant current source 22 to form a mirror circuit, P channel transistors (hereinafter referred to as P transistors) 25a and 25b connected to a power line 24 to form a constant current source, P transistors 26a and 26b functioning as switches for logic output, and terminating resistors 28a and 28b connected to a ground line 27.
The P transistors 26a and 26b include gates connected to input terminals 21a and 21b, respectively, and drains connected to the terminating resistors 28a and 28b, respectively. Further, sources of the P transistors 26a and 26b are connected to the drain of the P transistor 25b, and the output terminals 29a and 29b are connected between the P transistor 26a and the terminating resistor 28a, and between the P transistor 26b and the terminating resistor 28b, respectively. Differential logic signals inside an LSI ARE input through the input terminals 21a and 21b, and voltage values determined by current values flowing in the P transistors 26a and 26b and resistance values of the terminating resistors 28a and 28b are output from the output terminals 29a and 29b as logic amplitude.
The differential receiver block 30 includes a differential comparator 33, and terminating resistors 35a and 35b connected between two inputs of the differential comparator 33 and a ground line 34. The differential outputs from the output terminals 29a and 29b of the differential transmitter block 20 are input to the differential comparator 33 through the input terminals 31a and 31b, and the logic signal determined by the difference of the symbols is output from an output terminal 36.
The idle state detector block 40 includes a pair of differential comparators 41a and 41b, and a logic NOR circuit 42 to which the outputs of the differential comparators 41a and 41b are input. Positive logic input sides of the differential comparators 41a and 41b are connected to the input terminals 31a and 31b, respectively, and negative logic input sides thereof are connected to a reference voltage input terminal 44 to which the reference voltage for determining idle state is input.
The idle state detector block 40 thus configured compares the signal levels of the input terminals 31a and 31b with the reference voltage, and determines that there is no data transmission and reception performed between the differential transmitter block 20 and the differential receiver block 30, which means the differential transceiver is in the idle state on a condition that any signal level of the input terminals is lower than the reference voltage, so as to output the Hi logic output indicating it from a determination terminal 43.
In the differential transceiver including the terminating resistor provided therein, if the logic output in the transmitting side (differential transmitter block 20 side) is fixed when there is no data transmitted or received, current is consumed constantly due to the presence of the terminating resistor. According to the differential transceiver shown in FIG. 7, it is possible to prevent power consumption in the idle state by turning off the P transistors 26a and 26b and setting the output to Hi-Z (high impedance) state when there is no data transmitted or received.
Further, since the discharge is generated through the terminating resistors in the transmitting and receiving sides in the idle state, any signal level of the input terminals 31a and 31b is Low. In this case, the receiving side (differential receiver block 30 side) may respond to small potential difference due to the influence of the noise in the actual operation and may accidentally receive the signal. In the differential transceiver shown in FIG. 7, it is possible to prevent accidental receiving of the signal at the receiving side by detecting the idle state which is different from the normal transmitting or receiving state of the data by the idle state detector block 40.
FIG. 8 shows another example of the transmitting side of the differential transceiver including the terminating resistors. Note that the same components as those of the differential transceiver shown in FIG. 7 are denoted by the same symbols, and the overlapping description thereof will be omitted.
As shown in FIG. 8, a differential transmitter block 50 includes a switch 54 capable of turning on or off the connection between the power line 24 and the gate of the P transistor 25b forming the constant current source, and a switch 58 capable of turning on or off the connection between the gate of the P transistor 25a, and the drain of the p transistor 25a and the N transistor 23b. These two switches are controlled to be turned on or off complementarily by a control signal from a control terminal 51. More specifically, the switch 54 is turned off and the switch 58 is turned on when the data is transmitted, whereas the switch 54 is turned on and the switch 58 is turned off in the idle state. Accordingly, the P transistor 25b which is the driver current source is turned off and the current flowing in the P transistors 26a and 26b reduces in the idle state. Hence, the power consumption in the terminating resistor in the idle state can be reduced.
Japanese Unexamined Patent Application Publication No. 10-209830 discloses a technique for reducing power consumption by disconnecting a terminating resistor in the idle state. In FIG. 9, a symbol 7 is added to the ground line with respect to FIG. 1 of Japanese Unexamined Patent Application Publication No. 10-209830, and the technique thereof will be described with reference to FIG. 9.
An input interface circuit 10 shown in FIG. 9 includes a sampling circuit 4 sampling a signal from an input connecting point 1, and a terminating resistor 3. Further, a switching element 2 whose ON/OFF is controlled by a sampling control signal 5 is provided between the sampling circuit 4 or the terminating resistor 3 and the input connecting point. A power supply voltage is applied to the sampling circuit 4 through the input connecting point 1 and the switching element 2. Since the input impedance of the sampling circuit 4 is normally a large value, most of the current i flowing in the input connecting point 1 and the switching element 2 flows in the terminating resistor 3. Accordingly, the current i flowing in the input connecting point and the switching element 2 is determined by a resistance value of the terminating resistor 3. The sampling circuit 4 performs sampling on the voltage applied according to the sampling control signal 5, so as to detect ON/OFF of the input connecting point 1. When the input connecting point 1 is in ON state, the power supply voltage is applied to the input of the sampling circuit 4, so that the sampling circuit 4 outputs Hi level signal as the sampling value 6. When the input connecting point is in OFF state, the power supply voltage is not applied to the input of the sampling circuit 4, so that the sampling circuit 4 outputs the Low level signal as the sampling value 6. The switching element 2 is turned on when the sampling control signal 5 is input in accordance with the sampling control signal 5, and is otherwise turned off. Accordingly, the switching element 2 is turned on and the current flows only when the sampling circuit 4 performs sampling, and otherwise the switching element 2 is in OFF state and the current does not flow. According to this configuration, the power consumed in the terminating resistor 3 can be reduced.
In recent years, the volume of the data has become larger and the transmission speed has been increased. Accordingly, there is a growing demand to reduce power consumption of the transceiver. For example, the memory modules have been connected to each other by a plurality of lanes in order to transmit large volumes of data in higher speed. In case of the FB-DIMM, it is required by the standard to connect high-speed serial interface in parallel to connect adjacent modules by 24 lanes. In a transmission path having a terminating resistor provided for impedance matching in each lane, power consumption of the terminating resistor increases as the number of lanes increases, which requires further reduce of the power consumption of the terminating resistor in the idle state.
In the differential transceiver shown in FIG. 7, the output of the differential transmitter block 20 is in Hi-Z state in the idle state, so as to reduce power consumption of the terminating resistor. Accordingly, the signal levels of the two output terminals of the differential transmitter block 20 are Low in the idle state, which requires a reference voltage for detecting the idle state to prevent the false reception. Since there is a need to determine the idle state by fully considering a noise margin in order to correspond to the signal having small amplitude, this reference voltage needs to be highly accurate and constant value without being influenced by power supply fluctuation or temperature fluctuation. Therefore, a dedicated analog circuit for generating the reference voltage needs to be provided, which complicates the circuit design and increases the layout area.
In the differential transmitter block 50 shown in FIG. 8, the power consumption of the terminating resistor is reduced by reducing the current flowing in the P transistors 26a and 26b in the idle state. At this time, the differential transmitter block 50 is in the Hi-Z output state. Accordingly, as in the differential transceiver shown in FIG. 7, the reference voltage for detecting the idle state at the receiving side is required, which also causes the problem as described above.
In the input interface circuit 10 shown in FIG. 9, it is possible to reduce the power consumed at the terminating resistor 3 in the idle state. At this time, the input level to the sampling circuit 4 is in the level of the ground line 7, which means that the idle state and the logic “0” state of the signal input to the input interface 10 cannot be determined by the sampling value 6.